The trend for a number of years in fabrication of CMOS integrated circuits is toward fabrication of transistors having smaller geometries and thinner gate oxides. These smaller geometries permit faster operation of the circuits and provide for more efficient manufacturing by permitting larger numbers of circuits to be placed on each semiconductor wafer.
Unfortunately, this trend is not without disadvantages. For example, as the geometries of the circuits decrease, the ability of the circuit to withstand large rail-to-rail voltage swings diminishes and the thinner gate oxides of the individual transistor devices exhibit problems with tunneling at a lower voltage. This in turn complicates retention of a standard supply voltage for a particular device or generation of devices. Thus, in order to provide more advanced circuitry operating at higher speeds, more advanced CMOS devices (which are generally operated as rail-to-rail output logic devices) with smaller geometries have required circuitry to adapt to earlier established voltage supplies, or else a new generation of devices operating at lower supply voltages, had to be defined. Thus, in order to advance the state of the art, earlier defined standards on power supply voltage had to be abandoned in favor of newer standards, providing little stability of supply voltage requirements across process generations.